ARM AMBA NIC-301 Specifiche Scaricare il pdf (Pagina 91)

Programmers Model

ID062813 Non-Confidential

Table 3-20 shows the bit assignments.

Table 3-20 Test chip CFGREG14, 16, 18, 20, 22, 24 and 26 Register bit assignments

Bits Name Function

[31:12] - Reserved. Do not modify.

[11:8] x_CLKOD PLL output divider settings. Divisor = x_CLOD+1.

These bits have the following default values:

CFGREG14 - SYS PLL

b0001

CFGREG16 - DDR PLL

b0101

CFGREG18 - HDLCD PLL

b1101

CFGREG20 - A15 0 PLL

b0001

CFGREG22 - A15 1 PLL

b0001

CFGREG24 - A7 0 PLL

b0001

CFGREG26 - A7 0 PLL

b0001

See Test chip PLLs and clock divider logic on page 2-30.

Note

See Table 2-8 on page 2-28 for the maximum clock operating

frequencies.

[7:6] - Reserved. Do not modify.

[5:0] x_CLKR PLL reference clock divider settings. Divisor = x_CLKR+1.

These bits have the following default values:

CFGREG14 - SYS PLL

b001101

CFGREG16 - DDR PLL

b000011

CFGREG18 - HDLCD PLL

b001001

CFGREG20 - A15 0 PLL

b001101

CFGREG22 - A15 1 PLL

b001110

CFGREG24 - A7 0 PLL

b011100

CFGREG26 - A7 0 PLL

b010001

See Test chip PLLs and clock divider logic on page 2-30.

Note

See Table 2-8 on page 2-28 for the maximum clock operating

frequencies.

1 2 ... 86 87 88 89 90 91 92 93 94 95 96 ... 177 178

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ARM AMBA NIC-301 Specifiche Pagina 91

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