ARM AMBA NIC-301 Specifiche Pagina 13

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Introduction
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. 1-2
ID062813 Non-Confidential
1.1 About the CoreTile Express A15×2 A7×3 daughterboard
The CoreTile Express A15×2 A7×3 daughterboard is designed as a platform for developing
systems based on Advanced Microcontroller Bus Architecture (AMBA
®
) that use the Advanced
eXtensible Interface (AXI
) or custom logic for use with ARM cores.
You can use the CoreTile Express A15×2 A7×3 daughterboard to create prototype systems.
Note
You can use the CoreTile Express A15×2 A7×3 daughterboard with a Motherboard Express
µATX See System interconnect signals on page 2-6 for information about interconnection.
You can also use the CoreTile Express daughterboard with a custom-design motherboard. See
Programmer Module (V2M-CP1).
The daughterboard includes the following features:
Cortex-A15_A7 MPCore test chip, with NEON, the advanced Single Instruction Multiple
Data (SIMD) extension, and Floating Point Unit (FPU), that contains a dual-core A15
cluster operating at 1GHz and a triple-core A7 cluster operating at 800MHz.
Cortex-A15_A7 MPCore test chip internal AXI subsystem operating at 500MHz.
Simple configuration with V2M-P1 motherboard:
Configuration EEPROM.
Daughterboard Configuration Controller.
Nine programmable oscillators.
2GB of daughterboard DDR2 32-bit memory operating at 400MHz.
High Definition LCD (HDLCD) controller that supports up to 1920×1080p video at 60Hz,
165MHz pixel clock.
CoreSight software debug and 32-bit trace ports.
HDRX header with one multiplexed AMBA AXI master bus port that connects to the
other daughterboard site on the V2M-P1 motherboard.
HDRY header with four buses to the motherboard:
Static Memory Bus (SMB).
MultiMedia Bus (MMB).
Configuration Bus (CB).
System Bus (SB).
Power Supply Units (PSUs) for the Cortex-A15_A7 test chip and DDR2 memory.
Core voltage control and current, temperature, and power monitoring.
On-board energy meter.
Note
The Cortex-A15_A7 test chip does not support TrustZone
®
.
Figure 1-1 on page 1-3 shows the layout of the daughterboard:
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