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3.4.9 DDR2 memory controllers, DMC-400

The DMC-400 AXI interface runs asynchronously to the internal NIC-301 AXI interconnect,

by default, at the frequency that the daughterboard oscillator, OSCLK 8, defines. See:

• Top-level view of the Cortex-A15_A7 MPCore test chip components on page 2-4

• Figure 2-10 on page 2-26.

See the example

board.txt

file in the Versatile Express

™

Configuration Technical Reference

Manual for information on how to set OSCCLK 8.

Table 3-38 provides information on the DDR2 DMC-400 memory controller implementation.

ACE-Lite master port M0 Connects to the NIC-301 AXI subsystem

ACE-Lite master port M1 Connects to the DMC-400

ACE-Lite master port M2 Connects to the DMC-400

Release version ARM CCI-400 r0p2

Reference documentation

CoreLink

™

CCI-400 Cache Coherent Interconnect Technical Reference Manual

Table 3-37 cache controller implementation (continued)

Property Value

Table 3-38 DDR2 memory controllers implementation

Property Value

Memory base address Controller 0:

0x_00_2B0A_0000

System interfaces 2

System ID width 9

System address width 40

System data width 128

System read acceptance 32

System read hazard depth 8

System read hazard RAM 0

Memory interfaces 1

Memory data width 64

Memory chip selects 2

Write buffer depth 16

Write buffer RAM 0

Read queue depth 32

Maximum burst length 4

1 2 ... 110 111 112 113 114 115 116 117 118 119 120 ... 177 178

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