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HDLCD controller
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. B-3
ID062813 Non-Confidential
B.2 HDLCD Programmers Model
This section describes the programmers model. It contains the following subsections:
• About the HDLCD controller programmers model
• Register summary
• Register descriptions on page B-4.
B.2.1 About the HDLCD controller programmers model
The following information applies to the HDLCD controller registers:
• The base address is not fixed, and can be different for any particular system
implementation. The offset of each register from the base address is fixed.
• Do not attempt to access reserved or unused address locations. Attempting to access these
locations can result in
UNPREDICTABLE behavior.
• Unless otherwise stated in the accompanying text:
— Do not modify undefined register bits.
— Ignore undefined register bits on reads.
— All register bits are reset to a logic 0 by a system or power-on reset.
• Access type in Table B-1 is described as follows:
RW Read and write.
RO Read only.
WO Write only.
B.2.2 Register summary
Table B-1 shows the registers in offset order from the base memory address.The base memory
address of the HDLCD controller on the Cortex-A15 MPCore test chip is
0x00_2B00_0000
.
Table B-1 Register summary
Offset Name Type Reset Width Description
0x0000
VERSION RO VERSION 32 Version Register on page B-4
0x0010
INT_RAWSTAT RW
0x0
32 Interrupt Raw Status Register on page B-5
0x0014
INT_CLEAR WO N/A 32 Interrupt Clear Register on page B-6
0x0018
INT_MASK RW
0x0
32 Interrupt Mask Register on page B-7
0x001C
INT_STATUS RO
0x0
32 Interrupt Status Register on page B-8
0x0100
FB_BASE RW
0x0
32 Frame Buffer Base Address Register on page B-9
0x0104
FB_LINE_LENGTH RW
0x0
32 Frame Buffer Line Length Register on page B-9
0x0108
FB_LINE_COUNT RW
0x0
32 Frame Buffer Line Count Register on page B-10
0x010C
FB_LINE_PITCH RW
0x0
32 Frame Buffer Line Pitch Register on page B-11
0x0110
BUS_OPTIONS RW
0x408
32 Bus Options Register on page B-11
0x0200
V_SYNC RW
0x0
32 Vertical Synch Width Register on page B-12
0x0204
V_BACK_PORCH RW
0x0
32 Vertical Back Porch Width Register on page B-13
0x0208
V_DATA RW
0x0
32 Vertical Data Width Register on page B-13
- CoreTile 1
- Express A15×2 A7×3 1
- CoreTile Express A15×2 A7×3 2
- CE Declaration of Conformity 3
- Contents 4
- Appendix B HDLCD controller 5
- Appendix D Revisions 5
- • About this book on page vii 6
- • Feedback on page xi 6
- About this book 7
- Preface 10
- ID062813 Non-Confidential 10
- Feedback 11
- Chapter 1 12
- Introduction 12
- 1.2 Precautions 15
- Chapter 2 16
- Hardware Description 16
- MBM_nRST 29
- Internal resets 32
- 0x0000_0000 38
- 2.7 Clocks 39
- (CLKF + 1) 46
- (CLKOD + 1) (CLKR + 1)x 46
- 2.8 Interrupts 49
- 2.8.2 Interrupts 50
- 2.9 HDLCD 53
- 2.10 DDR2 memory interface 54
- 2.11 Debug 55
- Components Technical 56
- Reference Manual 56
- Chapter 3 58
- UNPREDICTABLE behavior 59
- 3.2 Daughterboard memory map 60
- You can access NOR 0 at 61
- and at 61
- 0x00_0000_0000 62
- 3.3 Test chip SCC registers 69
- SMC_ADDR_MATCH1_0 75
- SMC_ADDR_MASK1_0 75
- DMA_BOOT_ADDR 79
- DAP ROM Default Target ID 82
- DAP ROM Default Instance ID 83
- A15_CRNTCLK[3:0] 88
- A7_CRNTCLK[3:0] 88
- 31 16 15 8 0 92
- Programmers Model 100
- 0x000A50F5 to the 108
- Cortex-A15_A7 CPU ID 110
- 0x2A43_0000 119
- Reserved 120
- 0x2A80_0000 126
- CNTPL0ACR 136
- CNTP_TVAL 139
- CNTVL_CVAL 140
- Appendix A 147
- Signal Descriptions 147
- HDRXHDRY 148
- TRACE (DUAL) TRACE (SINGLE) 148
- Figure A-2 HSB multiplexing 149
- A.3 Header connectors 151
- Appendix B 155
- HDLCD controller 155
- B.1 Introduction 156
- B.2 HDLCD Programmers Model 157
- 31 16 15 8 7 0 158
- FB_BASE_ADDR 163
- FB_LINE_COUNT 164
- RESERVED 164
- FB_LINE_PITCH 165
- 31 12 11 0 167
- Reserved V_SYNC 167
- Reserved V_BACK_PORCH 167
- Reserved V_DATA 168
- Reserved V_FRONT_PORCH 168
- Reserved H_SYNC 169
- Reserved H_BACK_PORCH 169
- Reserved H_DATA 170
- Reserved H_FRONT_PORCH 170
- 31 30 5432 0 173
- BIG_ENDIAN 173
- BYTES_PER_PIXEL 173
- Appendix C 175
- Electrical Specifications 175
- C.1 AC characteristics 176
- Appendix D 177
- Revisions 177
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