ARM AMBA NIC-301 Specifiche Scaricare il pdf (Pagina 111)

Programmers Model

ID062813 Non-Confidential

3.4 Programmable peripherals and interfaces

The following sections describe the configurable modules in the test chip:

• Cortex-A15 cluster

• Cortex-A15 L2 cache controller

• Cortex-A7 cluster on page 3-55

• Cortex-A7 L2 cache controller on page 3-55

• GIC-400 Interrupt controller on page 3-56

• AXI network interconnect, NIC-301 on page 3-57

• HDLCD controller on page 3-57

• Cache Coherent Interconnect, CCI-400 on page 3-57

• DDR2 memory controllers, DMC-400 on page 3-58

• Static memory controller, PL354 on page 3-59

• Direct memory access controller, DMA-330 on page 3-60

• Watchdog, SP805 on page 3-60

• System counter on page 3-61

• System timer on page 3-75.

See also the reference manual for each peripheral for more information on programming these

devices.

3.4.1 Cortex-A15 cluster

The Cortex-A15 cluster, version r2p1, consists of two Cortex-A15 cores, with NEON media

processing technology, SIMD extension and FPU. The L1 memory subsystem has 32KB of

instruction cache and 32KB of data cache for each core.

For information about the programmable devices within the Cortex-A15 cluster, see the

Cortex

-A15 Technical Reference Manual.

3.4.2 Cortex-A15 L2 cache controller

Table 3-32 provides information on the Cortex-A15 Level-2 cache controller implementation.

Table 3-32 Cortex-A15 Level-2 cache controller implementation

Property Value

Memory base address Not applicable. The L2-cache controller is integrated into the Cortex-A15 cluster.

Cache size 1024KB.

Number of Ways 16.

Line size 64 bytes.

Master port Single 128-bit ACE interface.

Slave port Single 128-bit AXI 4 ACP interface.

Physically indexed and tagged cache -

Parity Error Correction Code (ECC), if enabled.

1 2 ... 106 107 108 109 110 111 112 113 114 115 116 ... 177 178

Nessun commento

ARM AMBA NIC-301 Specifiche Pagina 111