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Programmers Model
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. 3-49
ID062813 Non-Confidential
[15] CA7_EVENTSTREAM Recommends boot firmware or operating system action:
b0
Do not implement CA7 event stream
generation
b1
Implement CA7 event stream generation.
The default is
b1
.
This bit has no direct effect but when it is
b1,
it acts as a hint
to the software to enable a work-around for the
Cortex-A15_A7 defect which prevents delivery of events
between the CA15 and CA7 clusters when they operate at
certain combinations of OPPs.
To implement the work-around, the software uses the system
counter to generate periodic wake-up events. The software
implementation defines the frequency at which it generates
the wake-up events.
The software must enable event stream generation for each
core after a warm or cold reset.
[14] CA15_EVENTSTREAM Recommends boot firmware or operating system action:
b0
Do not implement CA15 event stream
generation
b1
Implement CA15 event stream generation.
The default is
b1
.
This bit has no direct effect but when it is
b1
, it acts as a hint
to the software to enable a work-around for the
Cortex-A15_A7 defect which prevents delivery of events
between the CA15 and CA7 clusters when they operate at
certain combinations of OPPs.
To implement the work-around, the software uses the system
counter to generate periodic wake-up events. The software
implementation defines the frequency at which it generates
the wake-up events.
The software must enable event stream generation for each
core after a warm or cold reset.
[13] NONBOOT_CLUSTER_PWRDWN_ENABLE Recommends boot firmware or operating system action:
b0
Do not power down the non-boot cluster.
b1
Power down the non-boot cluster.
The default is
b1
.
This bit has no direct effect but when it is
b1
it acts as a hint to
the software to power down the non-boot cluster early in the
cold boot process. Before it does this, the software must
ensure that another software entity, such as an operating
system, can power up the cluster at a later time.
This feature is relevant only if the Daughterboard
Configuration Controller powers up both the CA15 and CA7
clusters during cold reset of the CoreTile Express A15x2
A7x3 daughterboard.
Table 3-28 Test chip CFGREG48 Register bit assignments (continued)
Bits Name Function
- CoreTile 1
- Express A15×2 A7×3 1
- CoreTile Express A15×2 A7×3 2
- CE Declaration of Conformity 3
- Contents 4
- Appendix B HDLCD controller 5
- Appendix D Revisions 5
- • About this book on page vii 6
- • Feedback on page xi 6
- About this book 7
- Preface 10
- ID062813 Non-Confidential 10
- Feedback 11
- Chapter 1 12
- Introduction 12
- 1.2 Precautions 15
- Chapter 2 16
- Hardware Description 16
- MBM_nRST 29
- Internal resets 32
- 0x0000_0000 38
- 2.7 Clocks 39
- (CLKF + 1) 46
- (CLKOD + 1) (CLKR + 1)x 46
- 2.8 Interrupts 49
- 2.8.2 Interrupts 50
- 2.9 HDLCD 53
- 2.10 DDR2 memory interface 54
- 2.11 Debug 55
- Components Technical 56
- Reference Manual 56
- Chapter 3 58
- UNPREDICTABLE behavior 59
- 3.2 Daughterboard memory map 60
- You can access NOR 0 at 61
- and at 61
- 0x00_0000_0000 62
- 3.3 Test chip SCC registers 69
- SMC_ADDR_MATCH1_0 75
- SMC_ADDR_MASK1_0 75
- DMA_BOOT_ADDR 79
- DAP ROM Default Target ID 82
- DAP ROM Default Instance ID 83
- A15_CRNTCLK[3:0] 88
- A7_CRNTCLK[3:0] 88
- 31 16 15 8 0 92
- Programmers Model 100
- 0x000A50F5 to the 108
- Cortex-A15_A7 CPU ID 110
- 0x2A43_0000 119
- Reserved 120
- 0x2A80_0000 126
- CNTPL0ACR 136
- CNTP_TVAL 139
- CNTVL_CVAL 140
- Appendix A 147
- Signal Descriptions 147
- HDRXHDRY 148
- TRACE (DUAL) TRACE (SINGLE) 148
- Figure A-2 HSB multiplexing 149
- A.3 Header connectors 151
- Appendix B 155
- HDLCD controller 155
- B.1 Introduction 156
- B.2 HDLCD Programmers Model 157
- 31 16 15 8 7 0 158
- FB_BASE_ADDR 163
- FB_LINE_COUNT 164
- RESERVED 164
- FB_LINE_PITCH 165
- 31 12 11 0 167
- Reserved V_SYNC 167
- Reserved V_BACK_PORCH 167
- Reserved V_DATA 168
- Reserved V_FRONT_PORCH 168
- Reserved H_SYNC 169
- Reserved H_BACK_PORCH 169
- Reserved H_DATA 170
- Reserved H_FRONT_PORCH 170
- 31 30 5432 0 173
- BIG_ENDIAN 173
- BYTES_PER_PIXEL 173
- Appendix C 175
- Electrical Specifications 175
- C.1 AC characteristics 176
- Appendix D 177
- Revisions 177
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