Programmers Model

ID062813 Non-Confidential

Table 3-13 shows the bit assignments.

Table 3-13 Test chip CFGREG6 Register bit assignments

Bits Name Function

[31] PHY_IDDQ Forces the DDR PHY into IDDQ power-down mode:

DDR PHY enabled.

DDR PHY in IDDQ power-down mode.

The default is

[30] DDR_PHY_RESET_N PHY reset. Release after programming the PHY through APB and LOCK signal or register is

asserted:

Reset.

Non-reset.

The default is

[29] Reserved Reserved. Do not modify.

[28] A7_NVSOCRESET

Reset.

Non-reset.

The default is

. See Table 2-1 on page 2-15, Internal resets on page 2-17, and the

Cortex

-A7 MPCore

™

Technical Reference Manual.

[27] A7_NVCORERESET

Reset.

Non-reset.

The default is

. See Table 2-1 on page 2-15, Internal resets on page 2-17, and the

Cortex

-A7 MPCore

™

Technical Reference Manual.

[26] A7_NSOCDBGRESET

Reset.

Non-reset.

The default is

. See Table 2-1 on page 2-15, Internal resets on page 2-17.

[25] A7_NL2RESET Resets the A7 L2 logic, interrupt controller and timer logic. This reset operates independently

of nRESET:

Reset.

Non-reset.

The default is

. See Table 2-1 on page 2-15, Internal resets on page 2-17, and the

Cortex

-A7 MPCore

™

Technical Reference Manual.

[24:22] A7_NDBGRESET[2:0] This reset operates independently of nRESET:

Reset.

Non-reset.

The default is

b111

. See Table 2-1 on page 2-15, Internal resets on page 2-17, and the

Cortex

-A7 MPCore

™

Technical Reference Manual.

[21:19] A7_NETMRESET[2:0]

Reset.

Non-reset.

The default is

b111

. See Table 2-1 on page 2-15, Internal resets on page 2-17.

[18:16] A7_NCORERESET[2:0] This reset operates independently of nRESET:

Reset.

Non-reset.

The default is

b111

. See Table 2-1 on page 2-15, Internal resets on page 2-17, and the

Cortex

-A7 MPCore

™

Technical Reference Manual.

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