ARM AMBA NIC-301 Specifiche Pagina 102
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Programmers Model
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. 3-45
ID062813 Non-Confidential
Table 3-26 shows the bit assignments.
Test chip SCC Register 47
The CFGREG47 Register characteristics are:
Purpose Cache Coherency Interconnect, CCI-400, and DMC-400 configuration
register that enables you to read and write CCI-400 and DMC-400 port
configuration settings.
Table 3-26 Test chip CFGREG46 Register bit assignments
Bits Name Function
[31:25] - Reserved. Do not modify.
[24] NIDEN Maps to the NIDEN non-invasive debug enable signal:
b0
Disables non-invasive debug.
b1
Enables non-invasive debug. Enables the counting and export of
Process Monitor Unit (PMU) events.
The default is
b1
.
[23] SPNIDEN Maps to the SPNIDEN secure privileged non-invasive debug enable signal:
b0
Disables secure privileged non-invasive debug.
b1
Enables secure privileged non-invasive debug. Enables the
counting of both non-secure and secure PMU events.
The default is
b
1.
[22:19] ECOREVNUM[3:0] ECO revision number. The virtualizer software uses this data to read the
configuration of the system.
The default is
b0000
.
[18:14] ACCHANNELEN[4:0] Enables AC request on corresponding slave interface:
b0
Disables AC requests on slave interface.
b1
Enables AC requests on slave interface.
The default is
b11000
. Enable requests for Cortex-A15 and Cortex-A7 clusters, S3
and S4.
[13:9] QOSOVERRIDE4:0] Overrides the ARQOS and AW Q OS signals on the corresponding slave interface:
b0
Does not override the ARQOS and AWQOS signals.
b1
Overrides the ARQOS and AW QO S signals.
The default is
b00000
.
[8:6] BUFFERABLEOVERRIDE[2:0] Overrides the AWCACHE and ARCACHE[0] outputs to be non-bufferable. One
bit exists for each master interface. The default is
b000
.
[5:3] BARRIERTERMINATE[2:0] Terminates barriers instead of propagating on the corresponding master interface:
b0
Propagates barriers.
b1
Terminates barriers.
The default is
b111
.
[2:0] BROADCASTCACHEMAINT[2:0] Enables broadcasting of cache maintenance operations to downstream caches. Each
bit corresponds to one master interface:
b0
Disables broadcasting of cache maintenance operations to
downstream caches.
b1
Enables broadcasting of cache maintenance operations to
downstream caches.
The default is
b000
.
- CoreTile 1
- Express A15×2 A7×3 1
- CoreTile Express A15×2 A7×3 2
- CE Declaration of Conformity 3
- Contents 4
- Appendix B HDLCD controller 5
- Appendix D Revisions 5
- • About this book on page vii 6
- • Feedback on page xi 6
- About this book 7
- Preface 10
- ID062813 Non-Confidential 10
- Feedback 11
- Chapter 1 12
- Introduction 12
- 1.2 Precautions 15
- Chapter 2 16
- Hardware Description 16
- MBM_nRST 29
- Internal resets 32
- 0x0000_0000 38
- 2.7 Clocks 39
- (CLKF + 1) 46
- (CLKOD + 1) (CLKR + 1)x 46
- 2.8 Interrupts 49
- 2.8.2 Interrupts 50
- 2.9 HDLCD 53
- 2.10 DDR2 memory interface 54
- 2.11 Debug 55
- Components Technical 56
- Reference Manual 56
- Chapter 3 58
- UNPREDICTABLE behavior 59
- 3.2 Daughterboard memory map 60
- You can access NOR 0 at 61
- and at 61
- 0x00_0000_0000 62
- 3.3 Test chip SCC registers 69
- SMC_ADDR_MATCH1_0 75
- SMC_ADDR_MASK1_0 75
- DMA_BOOT_ADDR 79
- DAP ROM Default Target ID 82
- DAP ROM Default Instance ID 83
- A15_CRNTCLK[3:0] 88
- A7_CRNTCLK[3:0] 88
- 31 16 15 8 0 92
- Programmers Model 100
- 0x000A50F5 to the 108
- Cortex-A15_A7 CPU ID 110
- 0x2A43_0000 119
- Reserved 120
- 0x2A80_0000 126
- CNTPL0ACR 136
- CNTP_TVAL 139
- CNTVL_CVAL 140
- Appendix A 147
- Signal Descriptions 147
- HDRXHDRY 148
- TRACE (DUAL) TRACE (SINGLE) 148
- Figure A-2 HSB multiplexing 149
- A.3 Header connectors 151
- Appendix B 155
- HDLCD controller 155
- B.1 Introduction 156
- B.2 HDLCD Programmers Model 157
- 31 16 15 8 7 0 158
- FB_BASE_ADDR 163
- FB_LINE_COUNT 164
- RESERVED 164
- FB_LINE_PITCH 165
- 31 12 11 0 167
- Reserved V_SYNC 167
- Reserved V_BACK_PORCH 167
- Reserved V_DATA 168
- Reserved V_FRONT_PORCH 168
- Reserved H_SYNC 169
- Reserved H_BACK_PORCH 169
- Reserved H_DATA 170
- Reserved H_FRONT_PORCH 170
- 31 30 5432 0 173
- BIG_ENDIAN 173
- BYTES_PER_PIXEL 173
- Appendix C 175
- Electrical Specifications 175
- C.1 AC characteristics 176
- Appendix D 177
- Revisions 177
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