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HDLCD controller

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Interrupt Status Register

The INT_STATUS Register characteristics are:

Purpose Interrupt Raw Status Register on page B-5 ANDed with the Interrupt

Mask Register on page B-7 and shows the active and masked interrupt

sources. Bits selected by the Interrupt Mask Register on page B-7 are

active in the Interrupt Status Register. These bits show the status of the

interrupt sources. Bits not selected by the interrupt mask are inactive. If

any of the sources are asserted in the Interrupt Status Register, then the

external IRQ line is asserted.

Usage constraints There are no usage constraints.

Configurations Available in all HDLCD controller configurations.

Attributes See Table B-1 on page B-3.

Figure B-5 shows the bit assignments.

Figure B-5 Interrupt Status Register bit assignments

[2] VSYNC Vertical sync is active.

This interrupt triggers at the moment the VSYNC output goes active.

[1] BUS_ERROR The DMA module received a bus error while reading data.

This interrupt triggers if any frame buffer read operation ever reports an error.

[0] DMA_END The DMA module has finished reading a frame.

This interrupt triggers when the last piece of data for a frame has been read. The DMA

immediately continues on the next frame, so this interrupt only ensures that the frame buffer for

the previous frame is no longer required.

Table B-5 Interrupt Mask Register bit assignments (continued)

Bits Name Function

31 43 021

RESERVED

UNDERRUN

VSYNC

BUS_ERROR

DMA_END

1 2 ... 157 158 159 160 161 162 163 164 165 166 167 ... 177 178

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ARM AMBA NIC-301 Specifiche Pagina 162