
Signal Descriptions
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. A-5
ID062813 Non-Confidential
A.3 Header connectors
Two high-density headers are fitted to the underside of the daughterboard. Header HDRY, J2,
routes the buses and power interconnect between the V2P-CA15 daughterboard and the
V2M-P1 motherboard.
Header HDRX, J1, routes the HSB buses between the V2P-CA15_A7 daughterboard and the
daughterboard on the other motherboard site. The
an283_revc.ucf
constraints file, available in
application note AN283, Example LogicTile
™
Express 3MG design for a CoreTile
™
Express
A15×2, lists the HDRX signals.
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