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HDLCD controller

ID062813 Non-Confidential

Figure B-10 Bus Options Register bit assignments

Table B-11 shows the bit assignments.

Note

• If the scan line length does not end up at a multiple of the permitted burst lengths, the

controller uses smaller bursts to read the remaining few pixels in each scan line. If no

bursts are permitted, this mechanism also triggers, and has the same effect as permitting

all bursts.

• Incorrectly configuring this register can degrade the performance of both the LCD

controller and the rest of the system.

Vertical Synch Width Register

The V_SYNC Register characteristics are:

Purpose Holds the width of the vertical synch signal, counted in number of

horizontal scan lines.

Usage constraints There are no usage constraints.

Configurations Available in all HDLCD controller configurations.

31 1211 87 543210

Reserved

MAX_OUTSTANDING

Reserved

BURST_16

BURST_8

BURST_4

BURST_2

BURST_1

Table B-11 Bus Options Register bit assignments

Bits Name Function

[31:12] - Reserved, write as zero, read undefined.

[11:8] MAX_OUTSTANDING Maximum number of outstanding requests the LCD

controller is permitted to have on the bus at any time.

Caution

A value of zero disables all bus transfers.

[7:5] - Reserved, write as zero, read undefined.

[4] BURST_16 Permit the use of 16-beat bursts.

[3] BURST_8 Permit the use of 8-beat bursts.

[2] BURST_4 Permit the use of 4-beat bursts.

[1] BURST_2 Permit the use of 2-beat bursts.

[0] BURST_1 Permit the use of 1-beat bursts.

1 2 ... 161 162 163 164 165 166 167 168 169 170 171 ... 177 178

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ARM AMBA NIC-301 Specifiche Pagina 166