ARM AMBA NIC-301 Specifiche Pagina 78
- Pagina / 178
- Indice
- SEGNALIBRI
Valutato. / 5. Basato su recensioni clienti
Programmers Model
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. 3-21
ID062813 Non-Confidential
Test chip SCC Register 5
The CFGREG5 Register characteristics are:
Purpose DMA boot address register that enables you to read and write the address
of the boot instruction that the Dynamic Memory Access Controller,
(DMAC), DMA-330, executes when it exits from reset.
Usage constraints There are no usage constraints.
Configurations Not applicable.
Attributes See Table 3-6 on page 3-13.
Figure 3-10 on page 3-22 shows the bit assignments.
[24] DMA_BOOT_FRM_PC Boot from program counter. This controls the location from which the DMAC executes its
initial instruction after it exits from reset:
b0
DMAC waits for an instruction from the APB interface.
b1
DMAC executes the instruction that is located at the address that the DMA
boot address register provides.
The default is
b0
. See Test chip SCC Register 5 and the AMBA
®
DMA Controller DMA-330
Technical Reference Manual.
[23:10] - Reserved. Do not modify.
[9] CORESIGHT_SPNIDEN Maps to the SPNIDEN secure non-invasive debug signal for the CoreSight system.
The default is
b1
. See the ARM
®
CoreSight
™
Components Technical Reference Manual.
[8] CORESIGHT_NIDEN Maps to the NIDEN non-invasive debug enable signal for the CoreSight system.
The default is
b1
. See the ARM
®
CoreSight
™
Components Technical Reference Manual.
[7] CORESIGHT_SPIDEN Maps to the SPIDEN secure invasive debug signal for the CoreSight system.
The default is
b1
. See the ARM
®
CoreSight
™
Components Technical Reference Manual.
[6] CORESIGHT_ DBGEN Invasive debug enable for the CoreSight system:
b0
Disables invasive debug.
b1
Enables invasive debug.
The default is
b1
. See the ARM
®
CoreSight
™
Components Technical Reference Manual.
[5:4] SMC remap[1:0] These map to the SMC_REMAP[1:0] bus.
b00
Reserved.
b01
CS0.
b10
CS4.
b11
Reserved.
The default is
b01
. These bits are valid only if SMC is mapped to
0x00_0000_0000
, that is
CFGREG0[0] =
b0
.
[3:2] - Reserved. Do not modify.
[1:0] AXI_REMAP NIC-301 AMBA AXI memory map:
b00
SMC mapped to
0x00_0000_0000
. External AXI enabled.
b01
AXI Master interface mapped to
0x00_0000_0000
.
b10
SMC mapped to
0x00_0000_0000
. External AXI disabled.
The default is
b00
.
Table 3-11 Test chip CFGREG4 Register bit assignments (continued)
Bits Name Function
- CoreTile 1
- Express A15×2 A7×3 1
- CoreTile Express A15×2 A7×3 2
- CE Declaration of Conformity 3
- Contents 4
- Appendix B HDLCD controller 5
- Appendix D Revisions 5
- • About this book on page vii 6
- • Feedback on page xi 6
- About this book 7
- Preface 10
- ID062813 Non-Confidential 10
- Feedback 11
- Chapter 1 12
- Introduction 12
- 1.2 Precautions 15
- Chapter 2 16
- Hardware Description 16
- MBM_nRST 29
- Internal resets 32
- 0x0000_0000 38
- 2.7 Clocks 39
- (CLKF + 1) 46
- (CLKOD + 1) (CLKR + 1)x 46
- 2.8 Interrupts 49
- 2.8.2 Interrupts 50
- 2.9 HDLCD 53
- 2.10 DDR2 memory interface 54
- 2.11 Debug 55
- Components Technical 56
- Reference Manual 56
- Chapter 3 58
- UNPREDICTABLE behavior 59
- 3.2 Daughterboard memory map 60
- You can access NOR 0 at 61
- and at 61
- 0x00_0000_0000 62
- 3.3 Test chip SCC registers 69
- SMC_ADDR_MATCH1_0 75
- SMC_ADDR_MASK1_0 75
- DMA_BOOT_ADDR 79
- DAP ROM Default Target ID 82
- DAP ROM Default Instance ID 83
- A15_CRNTCLK[3:0] 88
- A7_CRNTCLK[3:0] 88
- 31 16 15 8 0 92
- Programmers Model 100
- 0x000A50F5 to the 108
- Cortex-A15_A7 CPU ID 110
- 0x2A43_0000 119
- Reserved 120
- 0x2A80_0000 126
- CNTPL0ACR 136
- CNTP_TVAL 139
- CNTVL_CVAL 140
- Appendix A 147
- Signal Descriptions 147
- HDRXHDRY 148
- TRACE (DUAL) TRACE (SINGLE) 148
- Figure A-2 HSB multiplexing 149
- A.3 Header connectors 151
- Appendix B 155
- HDLCD controller 155
- B.1 Introduction 156
- B.2 HDLCD Programmers Model 157
- 31 16 15 8 7 0 158
- FB_BASE_ADDR 163
- FB_LINE_COUNT 164
- RESERVED 164
- FB_LINE_PITCH 165
- 31 12 11 0 167
- Reserved V_SYNC 167
- Reserved V_BACK_PORCH 167
- Reserved V_DATA 168
- Reserved V_FRONT_PORCH 168
- Reserved H_SYNC 169
- Reserved H_BACK_PORCH 169
- Reserved H_DATA 170
- Reserved H_FRONT_PORCH 170
- 31 30 5432 0 173
- BIG_ENDIAN 173
- BYTES_PER_PIXEL 173
- Appendix C 175
- Electrical Specifications 175
- C.1 AC characteristics 176
- Appendix D 177
- Revisions 177
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