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Programmers Model

ID062813 Non-Confidential

Test chip SCC Register 48

The CFGREG48 Register characteristics are:

Purpose System information register that enables you to read and write Cortex-A15

and Cortex-A7 cluster system settings.

Usage constraints There are no usage constraints.

Configurations Not applicable.

Attributes See Table 3-6 on page 3-13.

Figure 3-26 on page 3-48 shows the bit assignments.

[17] CWAKEUP_S1 Disables DMC-400 S1 port clock gating.

Enables S1 port clock gating.

Disables S1 port clock gating.

The default is

[16] CWAKEUP_S0 Disables DMC-400 S0 port clock gating.

Enables S0 port clock gating.

Disables S0 port clock gating.

The default is

[15:12] AWREGIONS4[3:0] Writes region identifier on the CCI-400 S4 port. The Cortex-A15 cluster does not drive this signal:

Do not write region identifier.

Write region identifier.

The default is

b0000

[11:8] ARREGIONS4[3:0] Reads region identifier on CCI-400 S4 port. The Cortex-A15 cluster does not drive this signal:

Do not read region identifier.

Write read region identifier.

The default is

b0000

[7:4] AWREGIONS3[3:0] Writes region identifier on CCI-400 S3 port. The Cortex-A15 cluster does not drive this signal:

Do not write region identifier.

Write region identifier.

The default is

b0000

[3:0] ARREGIONS[3:0] Reads region identifier on CCI-400 S3 port. The Cortex-A15 cluster does not drive this signal:

Do not read region identifier.

Write read region identifier.

The default is

b0000

Table 3-27 Test chip CFGREG47 Register bit assignments (continued)

Bits Name Function

1 2 ... 99 100 101 102 103 104 105 106 107 108 109 ... 177 178

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