ARM ARM7TDMI Manuale Utente

Copyright © 1994-2001. All rights reserved.ARM DDI 0029GARM7TDMI(Rev 3)Technical Reference Manual

List of Tablesx Copyright © 1994-2001. All rights reserved. ARM DDI 0029GTable 4-3 Summary of coprocessor signaling ...

Memory Interface 3-30 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure 3-21 Typical system timingNote When designing a memory controlle

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-313.8 Action of ARM7TDMI core in debug stateWhen the ARM7TDMI core is in

Memory Interface 3-32 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G3.9 Privileged mode accessARM Limited usually recommends that if only p

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-333.10 Reset sequence after power upIt is good practice to reset a static

Memory Interface 3-34 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 4-1Chapter 4 Coprocessor InterfaceThis chapter describes the ARM7TDMI core coprocessor inter

Coprocessor Interface 4-2 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G4.1 About coprocessorsThe ARM7TDMI core instruction set enables you

Coprocessor Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 4-34.1.1 Coprocessor availabilityUp to 16 coprocessors can be referenc

Coprocessor Interface 4-4 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G4.2 Coprocessor interface signalsThe signals used to interface the

Coprocessor Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 4-54.3 Pipeline following signalsEvery coprocessor in the system must

List of TablesARM DDI 0029G Copyright © 1994-2001. All rights reserved. xiTable 7-22 APE control timing parameters ...

Coprocessor Interface 4-6 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G4.4 Coprocessor interface handshakingCoprocessor interface handshak

Coprocessor Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 4-74.4.2 The ARM7TDMI processorCoprocessor instructions progress down

Coprocessor Interface 4-8 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure 4-1 Coprocessor busy-wait sequenceCPA and CPB are ignored by

Coprocessor Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 4-9Caution It is essential that any action taken by the coprocessor wh

Coprocessor Interface 4-10 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G4.4.6 Coprocessor data operationsCoprocessor data operations, CDP

Coprocessor Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 4-11Figure 4-4 Coprocessor load sequenceADD SUB LDC n=4 TST SUBADD SUB

Coprocessor Interface 4-12 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G4.5 Connecting coprocessorsA coprocessor in an ARM7TDMI processor

Coprocessor Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 4-13Figure 4-6 Coprocessor connections with unidirectional busThe logi

Coprocessor Interface 4-14 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure 4-7 Connecting multiple coprocessorsARM coreCoprocessor1Cop

Coprocessor Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 4-154.6 If you are not using an external coprocessorIf you are impleme

List of Tablesxii Copyright © 1994-2001. All rights reserved. ARM DDI 0029G

Coprocessor Interface 4-16 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G4.7 Undefined instructionsUndefined instructions are treated by th

Coprocessor Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 4-174.8 Privileged instructionsThe output signal nTRANS allows the imp

Coprocessor Interface 4-18 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 5-1Chapter 5 Debug InterfaceThis chapter describes the ARM7TDMI processor debug interface. I

Debug Interface 5-2 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G5.1 About the debug interfaceThe ARM7TDMI processor debug interface is ba

Debug Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 5-3When the ARM7TDMI processor is in the debug state, the core is clocked by

Debug Interface 5-4 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G5.2 Debug systems Figure 5-1 shows a typical debug system using an ARM co

Debug Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 5-5The ARM7TDMI processor has hardware extensions that ease debugging at the

Debug Interface 5-6 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G5.3 Debug interface signalsThere are three primary external signals assoc

Debug Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 5-7Figure 5-3 Debug state entryEntry into debug state on breakpointThe ARM7T

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. xiiiList of FiguresARM7TDMI Technical Reference ManualFigure P-1 Key to timing diagram conve

Debug Interface 5-8 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G• An exception occurs, causing the processor to flush the instruction pip

Debug Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 5-95.3.2 Action of the processor in debug stateWhen the ARM7TDMI core enters

Debug Interface 5-10 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G5.4 ARM7TDMI core clock domainsThe ARM7TDMI clocks are described in Cloc

Debug Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 5-115.4.2 Clock switch during testWhen serial test patterns are being applie

Debug Interface 5-12 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G5.5 Determining the core and system stateWhen the core is in debug state

Debug Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 5-135.6 About EmbeddedICE LogicThe ARM7TDMI processor EmbeddedICE Logic prov

Debug Interface 5-14 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GThe EmbeddedICE Logic comprises:• two real-time watchpoint units• two in

Debug Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 5-155.7 Disabling EmbeddedICEThe EmbeddedICE Logic is disabled by setting DB

Debug Interface 5-16 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G5.8 Debug Communications ChannelThe ARM7TDMI processor EmbeddedICE Logic

Debug Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 5-17The function of each register bit is as follows:Bits 31:28 Contain a fi

List of Figuresxiv Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure 3-11 External bus arrangement ...

Debug Interface 5-18 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GSending a message to the debuggerWhen the processor has to send a messag

Debug Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 5-19• the DCC data write register is empty and available for use.These outpu

Debug Interface 5-20 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-1Chapter 6 Instruction Cycle TimingsThis chapter describes the ARM7TDMI processor instruct

Instruction Cycle Timings 6-2 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G• Coprocessor register transfer, store to coprocessor on page 6

Instruction Cycle Timings ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-36.1 About the instruction cycle timing tablesIn the following t

Instruction Cycle Timings 6-4 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G6.2 Branch and branch with linkA branch instruction calculates

Instruction Cycle Timings ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-56.3 Thumb branch with linkA Thumb Branch with Link operation co

Instruction Cycle Timings 6-6 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G6.4 Branch and ExchangeA Branch and Exchange (BX) operation tak

Instruction Cycle Timings ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-76.5 Data operationsA data operation executes in a single datapa

List of FiguresARM DDI 0029G Copyright © 1994-2001. All rights reserved. xvFigure 7-23 APE control timing ...

Instruction Cycle Timings 6-8 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GNote The shifted register operations where the destination is t

Instruction Cycle Timings ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-96.6 Multiply and multiply accumulateThe multiply instructions u

Instruction Cycle Timings 6-10 Copyright © 1994-2001. All rights reserved. ARM DDI 0029Gm+1 pc+12 0 2 - 1 0 1m+2 pc+12 0 2 - 0 1 1pc+12Table 6-7 Multi

Instruction Cycle Timings ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-11Note The multiply accumulate, multiply long, and multiply accu

Instruction Cycle Timings 6-12 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G6.7 Load registerThe first cycle of a load register instructio

Instruction Cycle Timings ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-13Note Operations where the destination is the PC are not availa

Instruction Cycle Timings 6-14 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G6.8 Store registerThe first cycle of a store register instruct

Instruction Cycle Timings ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-156.9 Load multiple registersThe first cycle of the LDM instruct

Instruction Cycle Timings 6-16 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GSingle register dest=pc 1 pc+2L i 0 (pc+2L) 0 0 02alu 2 0pc’ 1

Instruction Cycle Timings ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-176.10 Store multiple registersThe store multiple instruction pr

List of Figuresxvi Copyright © 1994-2001. All rights reserved. ARM DDI 0029G

Instruction Cycle Timings 6-18 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G6.11 Data swapThis is similar to the load and store register i

Instruction Cycle Timings ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-196.12 Software interrupt and exception entryExceptions (includi

Instruction Cycle Timings 6-20 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G6.13 Coprocessor data operationA coprocessor data operation is

Instruction Cycle Timings ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-216.14 Coprocessor data transfer from memory to coprocessorFor c

Instruction Cycle Timings 6-22 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GNote Coprocessor data transfer operations are not available in

Instruction Cycle Timings ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-236.15 Coprocessor data transfer from coprocessor to memoryThe A

Instruction Cycle Timings 6-24 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GNote Coprocessor data transfer operations are not available in

Instruction Cycle Timings ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-256.16 Coprocessor register transfer, load from coprocessorThe b

Instruction Cycle Timings 6-26 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G6.17 Coprocessor register transfer, store to coprocessorThis i

Instruction Cycle Timings ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-276.18 Undefined instructions and coprocessor absentWhen the pro

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. xviiPrefaceThis preface introduces the ARM7TDMI core and its reference documentation. It con

Instruction Cycle Timings 6-28 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G6.19 Unexecuted instructionsAny instruction whose condition co

Instruction Cycle Timings ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 6-296.20 Instruction speed summaryDue to the pipelined architectur

Instruction Cycle Timings 6-30 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GMULL S+(m+1)I -MLAL S+(m+2)I -CDP S+bI -LDC, STC (n-1)S+2N+bI

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-1Chapter 7 AC and DC ParametersThis chapter gives the AC timing parameters of the ARM7TDMI

AC and DC Parameters 7-2 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G• Test clock and external clock timing on page 7-21• Memory clock ti

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-37.1 Timing diagram informationEach timing diagram in this chapter is

AC and DC Parameters 7-4 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G7.2 General timingFigure 7-1 shows the ARM7TDMI general timing. The

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-5Note In Figure 7-1 on page 7-4, nWAIT, APE, ALE, and ABE are all HIG

AC and DC Parameters 7-6 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G7.3 Address bus enable controlFigure 7-2 shows the ARM7TDMI ABE cont

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-77.4 Bidirectional data write cycleFigure 7-3 shows the ARM7TDMI proc

Preface xviii Copyright © 1994-2001. All rights reserved. ARM DDI 0029GAbout this documentThis document is a reference manual for the ARM7TDMI core.In

AC and DC Parameters 7-8 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G7.5 Bidirectional data read cycleFigure 7-4 shows the ARM7TDMI proce

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-97.6 Data bus controlFigure 7-5 shows the ARM7TDMI data bus control t

AC and DC Parameters 7-10 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G7.7 Output 3-state timingFigure 7-6 shows the ARM7TDMI processor ou

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-117.8 Unidirectional data write cycle timingFigure 7-7 shows the ARM7

AC and DC Parameters 7-12 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G7.9 Unidirectional data read cycle timingFigure 7-8 shows the ARM7T

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-137.10 Configuration pin timingFigure 7-9 shows the ARM7TDMI processo

AC and DC Parameters 7-14 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G7.11 Coprocessor timingFigure 7-10 shows the ARM7TDMI processor cop

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-157.12 Exception timingFigure 7-11 shows the ARM7TDMI processor excep

AC and DC Parameters 7-16 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G7.13 Synchronous interrupt timingFigure 7-12 shows the ARM7TDMI pro

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-177.14 Debug timingFigure 7-13 shows the ARM7TDMI processor synchrono

Preface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. xixTypographical conventionsThe following typographical conventions are used in this

AC and DC Parameters 7-18 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GTrghRANGEOUT0, RANGEOUT1 hold time from MCLKf MinimumTrqhDBGRQ guar

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-197.15 Debug communications channel output timingFigure 7-14 shows th

AC and DC Parameters 7-20 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G7.16 Breakpoint timingFigure 7-15 shows the ARM7TDMI processor sync

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-217.17 Test clock and external clock timingFigure 7-16 shows the ARM7

AC and DC Parameters 7-22 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G7.18 Memory clock timingFigure 7-17 shows the ARM7TDMI processor me

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-237.19 Boundary scan general timingFigure 7-18 shows the ARM7TDMI pro

AC and DC Parameters 7-24 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G7.20 Reset period timingFigure 7-19 shows the ARM7TDMI reset period

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-257.21 Output enable and disable timesFigure 7-20 shows the output en

AC and DC Parameters 7-26 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G7.22 Address latch enable controlFigure 7-22 shows the ARM7TDMI res

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-277.23 Address pipeline control timingFigure 7-23 shows the ARM7TDMI

ii Copyright © 1994-2001. All rights reserved. ARM DDI 0029GARM7TDMITechnical Reference ManualCopyright © 1994-2001. All rights reserved.Release Info

Preface xx Copyright © 1994-2001. All rights reserved. ARM DDI 0029GTiming diagram conventionsThe key provided in Figure P-1 explains the components u

AC and DC Parameters 7-28 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G7.24 Notes on AC ParametersTable 7-23 lists the AC timing parameter

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-29TbrksSet up time of BREAKPT to MCLKr Minimum Figure 7-13TbschTCK hi

AC and DC Parameters 7-30 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GTcpihnCPI hold time from MCLKf Minimum Figure 7-10TcpmsCPA, CPB to

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-31TdoutMCLKf to D[31:0] valid Maximum Figure 7-3Figure 7-5TdoutuMCLKf

AC and DC Parameters 7-32 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GTrghRANGEOUT0, RANGEOUT1 hold time from MCLKf Minimum Figure 7-13Tr

AC and DC Parameters ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 7-33TtrstdnTRSTf to every output valid Maximum -TtrstdnTRSTf to TAP out

AC and DC Parameters 7-34 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G7.25 DC parametersContact your supplier for information on:• operat

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. A-1Appendix A Signal DescriptionThis appendix lists and describes the signals for the ARM7TD

Signal Description A-2 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GA.1 Signal descriptionThis section describes all of the signals for th

Signal Description ARM DDI 0029G Copyright © 1994-2001. All rights reserved. A-3A.1.3 Signals Table A-3 lists and describes all of the signals used fo

Preface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. xxiFurther readingThis section lists publications by ARM Limited and third parties.A

Signal Description A-4 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GBL[3:0]Byte latch controlIC The values on the data bus are latched on

Signal Description ARM DDI 0029G Copyright © 1994-2001. All rights reserved. A-5CPBCoprocessor busyIC Placed LOW by the coprocessor when it is ready t

Signal Description A-6 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GDOUT[31:0]Data output busO8 Unidirectional bus used to transfer data f

Signal Description ARM DDI 0029G Copyright © 1994-2001. All rights reserved. A-7IR[3:0]TAP controller instruction registerO4 Reflects the current inst

Signal Description A-8 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GnENOUTNot enable outputO4 During a write cycle, this signal is driven

Signal Description ARM DDI 0029G Copyright © 1994-2001. All rights reserved. A-9nRESETNot resetIC Used to start the processor from a known address.A L

Signal Description A-10 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GRANGEOUT0EmbeddedICE RANGEOUT0O4 When the EmbeddedICE watchpoint unit

Signal Description ARM DDI 0029G Copyright © 1994-2001. All rights reserved. A-11TAPSM[3:0]TAP controller state machineO4 These reflect the current st

Signal Description A-12 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-1Appendix B Debug in DepthThis appendix describes the debug features of the ARM7TDMI core

Preface xxii Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFeedbackARM Limited welcomes feedback both on the ARM7TDMI core, and on the docu

Debug in Depth B-2 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G• Coupling breakpoints and watchpoints on page B-52• EmbeddedICE timing on

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-3B.1 Scan chains and JTAG interfaceThere are three JTAG-style scan chains w

Debug in Depth B-4 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure B-1 ARM7TDMI core scan chain arrangementsScan chain 0Scan chain 0 e

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-5B.1.2 TAP state machineThe process of serial test and debug is best explai

Debug in Depth B-6 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.2 Resetting the TAP controllerThe boundary-scan (JTAG) interface include

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-7B.3 Pullup resistorsThe IEEE 1149.1 standard implies that nTRST, TDI, and

Debug in Depth B-8 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.4 Instruction registerThe instruction register is 4 bits in length. Ther

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-9B.5 Public instructionsTable B-1 lists the public instructions.In the foll

Debug in Depth B-10 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GThe EXTEST instruction connects the selected scan chain between TDI and T

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-11B.5.5 CLAMP (0101)This instruction connects a 1 bit shift register, the B

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 1-1Chapter 1 IntroductionThis chapter introduces the ARM7TDMI core. It contains the followin

Debug in Depth B-12 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.5.8 INTEST (1100)The INTEST instruction places the selected scan chain

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-13When the BYPASS instruction is loaded into the instruction register, all

Debug in Depth B-14 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.6 Test data registersThere are seven test data registers that can conne

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-15The 32-bit device identification code is loaded into the ID register from

Debug in Depth B-16 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GTAPSM[3:0], TCK1, and TCK2.The list of scan chain numbers allocated by AR

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-17• SHIFT.For input cells, the capture stage involves copying the value of

Debug in Depth B-18 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G• In SYSTEM mode, the scan cells are idle. System data is applied to inpu

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-19• During UPDATE-DR, the value shifted into the data bus D[31:0] scan cell

Debug in Depth B-20 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GTo access this serial register, scan chain 2 must first be selected using

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-21The following scan chain control signals can also be used for scan chain

Introduction 1-2 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G1.1 About the ARM7TDMI coreThe ARM7TDMI core is a member of the ARM family o

Debug in Depth B-22 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.7 The ARM7TDMI core clocksThe ARM7TDMI core has two clocks:• the memory

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-232. At this point, RESTART must be clocked into the TAP instruction regist

Debug in Depth B-24 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.8 Determining the core and system stateWhen the ARM7TDMI core is in deb

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-25The instruction in Example B-1 on page B-24 causes the contents of the re

Debug in Depth B-26 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.8.2 Determining system stateTo meet the dynamic timing requirements of

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-27Bit 33 of scan chain 1 is used to force the ARM7TDMI core to resynchroniz

Debug in Depth B-28 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure B-6 Debug exit sequenceYou can see from Figure 5-3 on page 5-7 tha

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-29B.9 Behavior of the program counter during debugThe debugger must keep tr

Debug in Depth B-30 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GDebug entry adds four addresses to the PC and every instruction adds one

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-310 E1A00000; MOV R0, R01 E1A00000; MOV R0, R00 EAFFFFFA; B -6This code res

Introduction ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 1-3Figure 1-1 Instruction pipelineDuring normal operation, while one instructio

Debug in Depth B-32 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.10 Priorities and exceptionsWhen a breakpoint, or a debug request occur

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-33B.11 Scan chain cell dataThis section provides data for:• Scan chain 0 ce

Debug in Depth B-34 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G20 D[19] Input/output21 D[20] Input/output22 D[21] Input/output23 D[22] I

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-3545DCTLaOutput46 nRW Output47 DBGACK Output48 CGENDBGACK Output49 nFIQ Inp

Debug in Depth B-36 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G70 ABE Input71 APE Input72 TBIT Output73 nWAIT Input74 A[31] Output75 A[3

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-37B.11.2 Scan chain 1 cellsThe ARM7TDMI core provides data for scan chain 1

Debug in Depth B-38 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G6 D[5] Input/output7 D[6] Input/output8 D[7] Input/output9 D[8] Input/out

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-3931 D[30] Input/output32 D[31] Input/output33 BREAKPT InputTable B-4 Scan

Debug in Depth B-40 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.12 The watchpoint registersThe two watchpoint units, known as Watchpoin

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-41B.12.1 Programming and reading watchpoint registersA watchpoint register

Introduction 1-4 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G1.1.3 Memory interfaceThe ARM7TDMI processor memory interface has been desig

Debug in Depth B-42 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GThe data to be written is shifted into the 32-bit data field. The address

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-43The bits have the following functions:nRW Compares against the write sig

Debug in Depth B-44 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GIn the ARM7TDMI core EmbeddedICE Logic, the RANGEOUT output of Watchpoint

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-45B.13 Programming breakpoints Breakpoints are classified as hardware break

Debug in Depth B-46 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.13.2 Software breakpointsTo make a watchpoint unit cause software break

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-47B.14 Programming watchpointsTo make a watchpoint unit cause watchpoints o

Debug in Depth B-48 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.15 The debug control registerThe debug control register is 3 bits wide.

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-49In the case of DBGACK, the value of DBGACK from the core is ORed with the

Debug in Depth B-50 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.16 The debug status registerThe debug status register is 5 bits wide. I

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-51Figure B-11 Debug control and status register structureBit 4Bit 3Bit 2Bit

Introduction ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 1-51.2 ArchitectureThe ARM7TDMI processor has two instruction sets:• the 32-bit

Debug in Depth B-52 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.17 Coupling breakpoints and watchpointsYou can couple watchpoint units

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-53The address comparator output of the watchpoint is used to drive the writ

Debug in Depth B-54 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.18 EmbeddedICE timingEmbeddedICE samples the EXTERN[1] and EXTERN[0] in

Debug in Depth ARM DDI 0029G Copyright © 1994-2001. All rights reserved. B-55B.19 Programming RestrictionThe EmbeddedICE Logic watchpoint units must o

Debug in Depth B-56 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. Glossary-1GlossaryThis glossary describes some of the terms used in this manual. Where terms

Glossary Glossary-2 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GBreakpoint A location in the image. If execution reaches this location,

Glossary ARM DDI 0029G Copyright © 1994-2001. All rights reserved. Glossary-3IRQ Interrupt request.Joint Test Action Group The name of the organizati

Glossary Glossary-4 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GAlso referred to as Current PSR (CPSR), to emphasize the distinction betw

Glossary ARM DDI 0029G Copyright © 1994-2001. All rights reserved. Glossary-5Status registers See Program Status Register.SP See Stack pointerSWI See

Introduction 1-6 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GThumb therefore offers a long branch range, powerful arithmetic operations,

Glossary Glossary-6 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. Index-1IndexThe items in this index are listed in alphabetical order, with symbols and numer

IndexIndex-2 Copyright © 1994-2001. All rights reserved. ARM DDI 0029Gcoprocessor register transfer 3-9internal 3-7merged I-S 3-8nonsequential

IndexARM DDI 0029G Copyright © 1994-2001. All rights reserved. Index-3state 3-31status register B-50system sppeed access B-31system state B-24

IndexIndex-4 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GProgram status register format 2-13ProgrammerÕs model 2-2Protocol converter

Introduction ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 1-71.3 Block, core, and functional diagramsThe ARM7TDMI processor architecture,

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. iiiConfidentiality StatusThis document is Open Access. This document has no restriction on

Introduction 1-8 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure 1-3 Main processorScan controlInstructiondecoder andlogic controlInst

Introduction ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 1-9Figure 1-4 ARM7TDMI processor functional diagram11DIN[31:0]ARM7TDMIMCLKnWAIT

Introduction 1-10 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G1.4 Instruction set summaryThis section provides a description of the instr

Introduction ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 1-11Refer to the ARM Architectural Reference Manual for more information about

Introduction 1-12 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GNote Some instruction codes are not defined but do not cause the Undefined

Introduction ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 1-13Multiply unsigned accumulate longUMLAL{cond}{S} RdLo, RdHi, Rm, RsMultiply

Introduction 1-14 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G• Decrement afterLDM{cond}DA Rd{!}, <reglist>{^}• Stack operationLDM{

Introduction ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 1-15Addressing modesThe addressing modes are procedures shared by different ins

Introduction 1-16 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GImmediate [Rn], #+/-12bit_OffsetRegister [Rn], +/-RmScaled register [Rn], +

Introduction ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 1-17Mode 3, <a_mode3> Immediate offset[Rn, #+/-8bit_Offset]Pre-indexed [R

iv Copyright © 1994-2001. All rights reserved. ARM DDI 0029G

Introduction 1-18 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GOperand 2An operand is the part of the instruction that references data or

Introduction ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 1-19Condition fieldsCondition fields are listed in Table 1-6.1.4.3 Thumb instru

Introduction 1-20 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure 1-6 Thumb instruction set formatsFormatFormatMove shifted registerMo

Introduction ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 1-21The Thumb instruction set summary is listed in Table 1-7. Table 1-7 Thumb i

Introduction 1-22 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GEOREOR Rd, RsORORR Rd, RsBit clearBIC Rd, RsMove NOTMVN Rd, RsTest bitsTST

Introduction ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 1-23UnconditionalB labelLong branch with linkBL labelOptional state change -• t

Introduction 1-24 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GWith register offset -• wordSTR Rd, [Rb, Ro]• halfwordSTRH Rd, [Rb, Ro]• by

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 2-1Chapter 2 Programmer’s ModelThis chapter describes the ARM7TDMI core programmer’s model.

Programmer’s Model 2-2 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G2.1 About the programmer’s modelThe ARM7TDMI processor core implements

Programmer’s Model ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 2-32.2 Processor operating statesThe ARM7TDMI processor has two operating

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. vContentsARM7TDMI Technical Reference ManualPrefaceAbout this document ...

Programmer’s Model 2-4 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G2.3 Memory formatsThe ARM7TDMI processor views memory as a linear coll

Programmer’s Model ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 2-52.3.2 Big-EndianIn big-endian format, the ARM7TDMI processor stores th

Programmer’s Model 2-6 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G2.4 Data typesThe ARM7TDMI processor supports the following data types

Programmer’s Model ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 2-72.5 Operating modesThe ARM7TDMI processor has seven modes of operation

Programmer’s Model 2-8 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G2.6 RegistersThe ARM7TDMI processor has a total of 37 registers:• 31 g

Programmer’s Model ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 2-9FIQ mode has seven banked registers mapped to r8–r14 (r8_fiq–r14_fiq).

Programmer’s Model 2-10 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G2.6.2 The Thumb-state register setThe Thumb-state register set is a s

Programmer’s Model ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 2-112.6.3 The relationship between ARM-state and Thumb-state registersThe

Programmer’s Model 2-12 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GNote Registers r0–r7 are known as the low registers. Registers r8–r1

Programmer’s Model ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 2-132.7 The program status registersThe ARM7TDMI processor contains a CPS

Contentsvi Copyright © 1994-2001. All rights reserved. ARM DDI 0029GChapter 3 Memory Interface3.1 About the memory interface ...

Programmer’s Model 2-14 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GAll instructions can execute conditionally in ARM state. In Thumb sta

Programmer’s Model ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 2-15Mode bitsBits M[4:0] determine the processor operating mode as shown

Programmer’s Model 2-16 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G2.8 ExceptionsExceptions arise whenever the normal flow of a program

Programmer’s Model ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 2-172.8.2 Entering an exceptionThe ARM7TDMI processor handles an exceptio

Programmer’s Model 2-18 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GNote Exceptions are always entered in ARM state. When the processor i

Programmer’s Model ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 2-192.8.5 Interrupt requestThe Interrupt Request (IRQ) exception is a nor

Programmer’s Model 2-20 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GPrefetch AbortWhen a Prefetch Abort occurs, the ARM7TDMI processor ma

Programmer’s Model ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 2-212.8.7 Software interrupt instructionThe Software Interrupt instructio

Programmer’s Model 2-22 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G2.8.10 Exception prioritiesWhen multiple exceptions arise at the same

Programmer’s Model ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 2-232.9 Interrupt latenciesThe calculations for maximum and minimum laten

ContentsARM DDI 0029G Copyright © 1994-2001. All rights reserved. vii6.14 Coprocessor data transfer from memory to coprocessor ...

Programmer’s Model 2-24 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G2.10 ResetWhen the nRESET signal goes LOW a reset occurs, and the ARM

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-1Chapter 3 Memory InterfaceThis chapter describes the ARM7TDMI processor memory interface.

Memory Interface 3-2 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G3.1 About the memory interfaceThe ARM7TDMI processor has a Von Neumann a

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-33.2 Bus interface signalsThe signals in the ARM7TDMI processor bus inter

Memory Interface 3-4 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G3.3 Bus cycle types The ARM7TDMI processor bus interface is pipelined. T

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-5Bus cycle types are encoded on the nMREQ and SEQ signals as listed in Ta

Memory Interface 3-6 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure 3-2 Nonsequential memory cycleThe ARM7TDMI processor can perform

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-7The possible burst types are listed in Table 3-2.All accesses in a burst

Memory Interface 3-8 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GWhere possible the ARM7TDMI processor broadcasts the address for the nex

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-9Figure 3-5 Merged IS cycleNote When designing a memory controller, ensur

Contentsviii Copyright © 1994-2001. All rights reserved. ARM DDI 0029GB.8 Determining the core and system state ...

Memory Interface 3-10 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure 3-6 Coprocessor register transfer cycles3.3.6 Summary of ARM mem

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-113.4 Addressing signalsThe address class signals are:• A[31:0] on page 3

Memory Interface 3-12 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GThe address produced by the processor is always a byte address. However

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-133.4.5 nTRANSThe nTRANS output conveys information about the transfer. A

Memory Interface 3-14 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G3.5 Address timingThe ARM7TDMI processor address bus can operate in one

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-15Note The AMBA specification for Advanced High-performance Bus (AHB) and

Memory Interface 3-16 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure 3-10 SRAM compatible address timingNote If ALE is to be used to

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-173.6 Data timed signalsThis section describes:• D[31:0], DOUT[31:0], and

Memory Interface 3-18 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure 3-12 Bidirectional bus timingUnidirectional data busWhen BUSEN i

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-19Figure 3-14 External connection of unidirectional busesBidirectional da

ARM DDI 0029G Copyright © 1994-2001. All rights reserved. ixList of TablesARM7TDMI Technical Reference ManualChange history ...

Memory Interface 3-20 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure 3-15 Data write bus cycleFigure 3-16 Data bus control circuitMCL

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-21The macrocell has an additional bus control signal, nENIN that allows t

Memory Interface 3-22 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GARM7TDMI core test chip example systemConnecting the ARM7TDMI processor

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-23Figure 3-17 Test chip data bus circuitNote At the core level, TBE and D

Memory Interface 3-24 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G3.6.2 ABORTABORT indicates that a memory transaction failed to complete

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-25Because two memory cycles are required, nWAIT is used to stretch the in

Memory Interface 3-26 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure 3-19 Two cycle memory access3.6.4 Byte and halfword accessesThe

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-27Note For subword reads the value is placed in the ARM register in the l

Memory Interface 3-28 Copyright © 1994-2001. All rights reserved. ARM DDI 0029GFigure 3-20 Data replication0A B C D7815162331 24ARMregisterHalf word w

Memory Interface ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 3-293.7 Stretching access timesThe ARM7TDMI processor does not contain any