ARM ARM7TDMI manuali

Arm ARM7TDMI Manuale Utente (284 pagine)

Marchio: Arm | Categoria: Processori | Dimensione: 1.74 MB |

Indice

ARM7TDMI

Contents

Chapter 3 Memory Interface

Chapter 5 Debug Interface

Appendix A Signal Description

Appendix B Debug in Depth

List of Tables

List of Figures

• Further reading on page xxi

• Feedback on page xxii

About this document

Preface

Further reading

Feedback

Chapter 1

Introduction

1.1 About the ARM7TDMI core

1.2 Architecture

Figure 1-3 Main processor

#32bit_Imm

[Rn, #+/-12bit_Offset]

[Rn, +/-Rm]

[Rn, #+/-8bit_Offset]

[Rn, #+/-(8bit_Offset*4)]

Operand 2

Chapter 2

Programmer’s Model

31 24 23 16 15 8 7 0

Word at address A

2.4 Data types

2.5 Operating modes

2.6 Registers

MOV PC, R14

MOVS PC, R14_svc

MOVS PC, R14_und

SUBS PC, R14_abt, #4

SUBS PC, R14_fiq, #4

SUBS PC, R14_irq, #4

SUBS PC, R14_abt, #8

SUBS PC,R14_fiq,#4

SUBS PC,R14_irq,#4

LDR Rn,[R14_abt,#-8]

SUBS PC,R14_abt,#4

SUBS PC,R14_abt,#8

0x00000004

0x00000008

0x0000000C

0x00000010

0x00000014

0x00000018

0x0000001C

2.9 Interrupt latencies

2.10 Reset

Chapter 3

3.2 Bus interface signals

3.3 Bus cycle types

Figure 3-4 Internal cycles

Figure 3-5 Merged IS cycle

3.4 Addressing signals

Table 3-5 nTRANS encoding

1 Privileged

3.5 Address timing

3.6 Data timed signals

DOUT[31:0]

XDATA[31:0]

DIN[31:0]

Figure 3-18 Memory access

Figure 3-20 Data replication

3.7 Stretching access times

Memory Interface

100

3.9 Privileged mode access

102

Figure 3-22 Reset sequence

103

Chapter 4

105

Coprocessor Interface

105

4.1 About coprocessors

106

Signal Direction Meaning

110

Table 4-2 Handshaking signals

110

ARM core

116

Coprocessor

116

4.7 Undefined instructions

120

4.8 Privileged instructions

121

Chapter 5

123

Debug Interface

123

5.1 About the debug interface

124

EmbeddedICE

127

Main processor

127

TAP controller

127

5.3 Debug interface signals

128

Figure 5-3 Debug state entry

129

MOV PC, #0

133

5.7 Disabling EmbeddedICE

137

MRC CP14, 0, Rd, C0, C0, 0

139

MCR CP14, 0, Rn, C1, C0, 0

139

MRC CP14, 0, Rd, C1, C0, 0

139

Chapter 6

143

Instruction Cycle Timings

143

SUB PC,R14,#4 to MOV PC,R14

146

6.3 Thumb branch with link

147

6.4 Branch and Exchange

148

6.5 Data operations

149

Thumb state

150

6.7 Load register

154

6.8 Store register

156

6.9 Load multiple registers

157

6.10 Store multiple registers

159

6.11 Data swap

160

6.19 Unexecuted instructions

170

Chapter 7

173

AC and DC Parameters

173

Figure 7-1 General timing

176

7.7 Output 3-state timing

182

7.10 Configuration pin timing

185

7.16 Breakpoint timing

192

TCK to ECLK delay Maximum

193

7.20 Reset period timing

196

In Table 7-23:

200

7.25 DC parameters

206

Appendix A

207

Signal Description

207

A.1 Signal description

208

A.1.3 Signals

209

Appendix B

219

Debug in Depth

219

Scan chain 2

222

B.1.2 TAP state machine

223

B.3 Pullup resistors

225

B.4 Instruction register

226

B.5 Public instructions

227

B.6 Test data registers

232

Figure B-4 Input scan cell

235

B.7 The ARM7TDMI core clocks

240

Internal cycles

246

0 E0802000; ADD R2, R0, R0

247

1 E1826001; ORR R6, R2, R1

247

MOV R0, R0

247

SUB PC, PC, #28

247

0 E1A00000; MOV R0, R0

248

1 E1A00000; MOV R0, R0

248

0 EAFFFFF0; B -16

248

0 EAFFFFFA; B -6

249

- (4+N+3S)

249

- (3+N+3S)

249

B.11 Scan chain cell data

251

B.11.2 Scan chain 1 cells

255

31 D[30] Input/output

257

32 D[31] Input/output

257

33 BREAKPT Input

257

Number Signal Type

257

B.12 The watchpoint registers

258

0xFFFFFFFF

260

B.13 Programming breakpoints

263

0xDEEEDEEE

264

0x00000000

264

B.14 Programming watchpoints

265

INTDIS DBGRQ DBGACK

266

B.18 EmbeddedICE timing

272

B.19 Programming Restriction

273

Glossary

275

Arm ARM7TDMI Manuale Utente (18 pagine)

Marchio: Arm | Categoria: Processori | Dimensione: 0.25 MB |

Indice

Development for ARM7TDMI

Processor Programmers

Arm ARM7TDMI Scheda Tecnica (42 pagine)

Marchio: Arm | Categoria: Processori | Dimensione: 0.37 MB |

Indice

ARM 7TDMI

Contents

Introduction

Open Access

ARM7TDMI

Signal Description

Programmer’s Model

= banked register

Arm ARM7TDMI Manuale Utente (242 pagine)

Marchio: Arm | Categoria: Processori | Dimensione: 1.41 MB |

Indice

ARM7TDMI-S

Contents

Chapter 3 Memory Interface

Chapter 6 ETM Interface

Chapter 8 AC Parameters

List of Tables

List of Figures

• Feedback on page xvi

About this document

Preface

Other publications

Architecture

Feedback

Chapter 1

Introduction

1.2 ARM7TDMI-S architecture

Figure 1-3 ARM7TDMI-S core

1.4.1 ARM instruction summary

[Rn, #+/-12bit_Offset]

[Rn, +/-Rm]

[Rn, #+/-12bit_Offset]!

[Rn, +/-Rm]!

, is shown in Table 1-4

[Rn, #+/-8bit_Offset]

[Rn, #+/-(8bit_Offset*4)]

Post-indexed

Fields

, are shown in Table 1-10

Condition fields

, are shown in Table 1-11

Halfword

POP <reglist>

POP <reglist, PC>

SWI 8bit_Imm

0x7F1F0F0F

Chapter 2

Programmer’s Model

2.3 Memory formats

2.4 Instruction length

2.5 Data types

2.6 Operating modes

2.7 Registers

Table 2-2 PSR mode bit values

MOV PC, R14

MOVS PC, R14_svc

MOVS PC, R14_und

SUBS PC, R14_abt, #4

SUBS PC, R14_fiq, #4

SUBS PC, R14_irq, #4

SUBS PC, R14_abt, #8

UNPREDICTABLE

SUBS PC,R14_fiq,#4

SUBS PC,R14_abt,#8

MOVS PC,R14_und

2.10 Interrupt latencies

2.11 Reset

Chapter 3

Memory Interface

3.2 Bus interface signals

3.3 Bus cycle types

Table 3-2 Burst types

Figure 3-5 Merged I-S cycle

3.4 Addressing signals

3.4.6 CPTBIT

3.5 Data timed signals

Figure 3-6 Data replication

Figure 3-7 Use of CLKEN

Chapter 4

4.1 About coprocessors

Table 4-2 Handshaking signals

Signal Direction Meaning

4.5 Connecting coprocessors

Coprocessor Interface

100

4.7 Undefined instructions

103

4.8 Privileged instructions

104

Chapter 5

105

Debugging Your System

105

5.2 Controlling debugging

109

5.3 Entry into debug state

111

Figure 5-3 Debug state entry

112

ARM7TDMI-Smacrocell

115

5.4 Debug interface

116

EmbeddedICE-RT

118

5.7 Disabling EmbeddedICE-RT

120

5.9 Monitor mode debugging

122

0 RW...100

124

MRC CP14, 0, Rd, C0, C0

125

MCR CP14, 0, Rn, C1, C0

125

MRC CP14, 0, Rd, C1, C0

126

5.12 The TAP controller

130

5.13 Public JTAG instructions

132

011112272831

135

Part number

135

Manufacturer identity 1

135

0x7f1f0f0f

136

5.15 Scan timing

140

31 DATA[30] Input/output

142

32 DATA[31] Input/output

142

33 DBGBREAK Input

142

Number Signal Type

142

5.17 Exit from debug state

146

0 E0802000; ADD R2, R0, R0

148

1 E1826001; ORR R6, R2, R1

148

MOV R0, R0

148

SUB PC, PC, #28

148

- (4 + N + 3S)

150

- (3 + N + 3S)

150

8 67 5 34 2 01

154

5.21 Programming breakpoints

157

0xffffffff

158

0xdfffdfff

158

0x00000000

158

5.22 Programming watchpoints

159

5.23 Abort status register

160

5.24 Debug control register

161

5.25 Debug status register

164

5.27 EmbeddedICE-RT timing

169

Chapter 6

171

ETM Interface

171

6.1 About the ETM interface

172

6.4 Clocks and resets

176

6.5 Debug request wiring

177

Chapter 7

179

Instruction Cycle Timings

179

MOV PC,R14

185

STM..{R14} LDM..{PC}

185

7.4 Thumb branch with link

186

7.5 Branch and exchange

187

7.6 Data operations

188

7.8 Load register

192

7.9 Store register

194

7.10 Load multiple registers

195

7.11 Store multiple registers

197

7.12 Data swap

198

7.20 Unexecuted instructions

208

Chapter 8

209

AC Parameters

209

8.1 Timing diagrams

210

Figure 8-2 Coprocessor timing

212

8.1.4 Debug timing

213

8.1.5 Scan timing

214

Figure 8-5 Scan timing

215

Appendix A

219

Signal Descriptions

219

A.1 Signal descriptions

220

Appendix B

227

ARM7TDMI

227

B.1 Interface signals

228

B.2 ATPG scan interface

232

B.3 Timing parameters

233

Arm ARM7TDMI Manuale Utente (43 pagine)

Marchio: Arm | Categoria: Processori | Dimensione: 0.13 MB |

Indice

ARM7TDMI

Instruction Set

Reference

Table of Contents

1 Instruction Encoding

2 Conditional Execution

3.1 General Notes

3.2 Shifter Operands

0 0 0 0 0 0 0 0 Rm

Rs 0 0 0 1 Rm

Rs 0 0 1 1 Rm

Rs 0 1 0 1 Rm

Rs 0 1 1 1 Rm

0 0 0 0 0 1 1 0 Rm

Page 10

Page 11

4 Instruction Descriptions

4.3 ADD - Add

4.4 AND – Bit-wise AND

Page 14

4.6 BIC – Bit Clear

4.8 CMN – Compare Negative

4.9 CMP - Compare

4.11 LDM – Load Multiple

Page 18

4.12 LDR – Load Register

4.18 MOV – Move

Page 23

4.21 MUL – Multiply

4.22 MVN – Move Negative

4.24 RSB – Reverse Subtract

4.29 STM – Store Multiple

Page 29

4.30 STR – Store Register

4.33 SUB - Subtract

4.35 SWP - Swap

4.36 SWPB – Swap Byte

4.37 TEQ – Test Equivalence

4.38 TST - Test

Page 35

5 Pseudo-Instructions

5.4 LDR – Load Register

5.7 NOP – No Operation

5.8 POP - Pop

5.9 PUSH - Push

5.10 ROR – Rotate Right

Page 39

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