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Directives Reference
7-14 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
7.3.1 LTORG
The
LTORG
directive instructs the assembler to assemble the current literal pool
immediately.
Syntax
LTORG
Usage
The assembler assembles the current literal pool at the end of every code section. The
end of a code section is determined by the
AREA
directive at the beginning of the
following section, or the end of the assembly.
These default literal pools can sometimes be out of range of some
LDR
,
LDFD
, and
LDFS
pseudo-instructions. See LDR ARM pseudo-instruction on page 4-82 and LDR Thumb
pseudo-instruction on page 5-41 for more information. Use
LTORG
to ensure that a literal
pool is assembled within range. Large programs can require several literal pools.
Place
LTORG
directives after unconditional branches or subroutine return instructions so
that the processor does not attempt to execute the constants as instructions.
The assembler word-aligns data in literal pools.
Example
AREA Example, CODE, READONLY
start BL func1
func1 ; function body
; code
LDR r1,=0x55555555 ; => LDR R1, [pc, #offset to Literal Pool 1]
; code
MOV pc,lr ; end function
LTORG ; Literal Pool 1 contains literal &55555555.
data SPACE 4200 ; Clears 4200 bytes of memory,
; starting at current location.
END ; Default literal pool is empty.
- Developer Suite 1
- ARM Developer Suite 2
- Contents 3
- • About this book on page vi 5
- • Feedback on page ix 5
- About this book 6
- Feedback 9
- Preface 10
- Introduction 11
- Chapter 1 11
- Chapter 2 13
- 2.1 Introduction 14
- MOV pc,lr 17
- Example 2-1 27
- Example 2-2 29
- Example 2-3 30
- 2.4 Using the C preprocessor 31
- 2.5 Conditional execution 32
- CMP r0, r1 35
- SUBGT r0, r0, r1 35
- SUBLT r1, r1, r0 35
- BNE gcd 35
- Example 2-5 40
- pseudo-instructions 41
- , where the 42
- Example 2-6 43
- Example 2-9 47
- Example 2-10 String copy 49
- -checkreglist 51
- STMFD (STMDB) LDMFD (LDMIA) 54
- STMFA (STMIB) LDMFA (LDMDA) 54
- STMED (STMDA) LDMED (LDMIB) 54
- STMEA (STMIA) LDMEA (LDMDB) 54
- ; code 55
- Example 2-11 Block copy 56
- Example 2-12 57
- Example 2-13 59
- 2.9 Using macros 60
- Example 2-14 61
- Example 2-15 62
- Example 2-16 64
- Example 2-17 65
- Example 2-18 66
- Example 2-19 67
- Example 2-20 68
- Example 2-21 69
- Example 2-22 72
- Example 2-23 72
- Example 2-24 73
- Example 2-25 74
- Example 2-26 75
- Example 2-27 76
- 2.11 Using frame directives 78
- Chapter 3 79
- 3.1 Command syntax 80
- -via file 85
- 3.2 Format of source lines 86
- 3.4 Built-in variables 88
- 3.5 Symbols 90
- Assembler Reference 100
- 3.6.10 Unary operators 104
- Table 3-10 Boolean operators 109
- Operator Usage Explanation 109
- Logical AND of A and B 109
- Logical OR of A and B 109
- Chapter 4 111
- ARM Instruction Reference 111
- 4.1 Conditional execution 114
- Figure 4-1 ROR 135
- Figure 4-2 RRX 136
- Architectures 145
- Examples 145
- Incorrect example 145
- 4.4 ARM multiply instructions 149
- Incorrect examples 151
- 4.6 ARM branch instructions 167
- SWI{cond} immed_24 182
- SWI 0x123456 182
- MSR CPSR_f, r5 185
- 4.9 ARM pseudo-instructions 188
- MOV r0, r0 194
- Chapter 5 195
- Thumb Instruction Reference 195
- PUSH {reglist} 205
- POP {reglist} 205
- PUSH {reglist, lr} 205
- POP {reglist, pc} 205
- 5.4 Thumb branch instructions 225
- BL label 228
- BL extract 228
- SWI immed_8 231
- SWI 12 231
- 5.6 Thumb pseudo-instructions 233
- MOV r8,r8 237
- Chapter 6 239
- 6.2 Floating-point registers 243
- 6.4 VFP and condition codes 246
- 6.5 VFP system registers 248
- 6.6 Flush-to-zero mode 251
- 6.7 VFP instructions 253
- FSTS s2, [r5] 262
- FLDS s9, fpconst 262
- FNMSCSLE s6, s0, s26 266
- 6.8 VFP pseudo-instruction 276
- Chapter 7 283
- Directives Reference 283
- Example 7-1 287
- Example 7-2 287
- WHILE...WEND 308
- IF...ELSE...ENDIF 308
- 7.6 Reporting directives 326
- 7.7 Miscellaneous directives 331
- Glossary 351
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