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Assembler Reference
3-24 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
3.6.9 Operator precedence
The assembler includes an extensive set of operators for use in expressions. Many of the
operators resemble their counterparts in high-level languages such as C (see Unary
operators on page 3-26 and Binary operators on page 3-28).
There is a strict order of precedence in their evaluation:
1. Expressions in parentheses are evaluated first.
2. Operators are applied in precedence order.
3. Adjacent unary operators are evaluated from right to left.
4. Binary operators of equal precedence are evaluated from left to right.
Note
The order of precedence is not exactly the same as in C.
For example,
(1 + 2 :SHR; 3)
evaluates as
(1 + (2 :SHR: 3))
= 1 in
armasm
. The
equivalent expression in C evaluates as
((1 + 2) >> 3)
= 0.
You are recommended to use brackets to make the precedence explicit.
Table 3-2 shows the order of precedence of operators in
armasm
, and a comparison with
the order in C.
If your code contains an expression which would parse differently in C,
armasm
normally
gives a warning:
A1466W: Operator precedence means that expression would evaluate differently in C
The warning is not given if you use the
-unsafe
command line option.
Table 3-2 Operator precedence in armasm
armasm precedence equivalent C operators
unary operators unary operators
* / :MOD
:
* / %
string manipulation n/a
:SHL: :SHR: :ROR: :ROL: << >>
- Developer Suite 1
- ARM Developer Suite 2
- Contents 3
- • About this book on page vi 5
- • Feedback on page ix 5
- About this book 6
- Feedback 9
- Preface 10
- Introduction 11
- Chapter 1 11
- Chapter 2 13
- 2.1 Introduction 14
- MOV pc,lr 17
- Example 2-1 27
- Example 2-2 29
- Example 2-3 30
- 2.4 Using the C preprocessor 31
- 2.5 Conditional execution 32
- CMP r0, r1 35
- SUBGT r0, r0, r1 35
- SUBLT r1, r1, r0 35
- BNE gcd 35
- Example 2-5 40
- pseudo-instructions 41
- , where the 42
- Example 2-6 43
- Example 2-9 47
- Example 2-10 String copy 49
- -checkreglist 51
- STMFD (STMDB) LDMFD (LDMIA) 54
- STMFA (STMIB) LDMFA (LDMDA) 54
- STMED (STMDA) LDMED (LDMIB) 54
- STMEA (STMIA) LDMEA (LDMDB) 54
- ; code 55
- Example 2-11 Block copy 56
- Example 2-12 57
- Example 2-13 59
- 2.9 Using macros 60
- Example 2-14 61
- Example 2-15 62
- Example 2-16 64
- Example 2-17 65
- Example 2-18 66
- Example 2-19 67
- Example 2-20 68
- Example 2-21 69
- Example 2-22 72
- Example 2-23 72
- Example 2-24 73
- Example 2-25 74
- Example 2-26 75
- Example 2-27 76
- 2.11 Using frame directives 78
- Chapter 3 79
- 3.1 Command syntax 80
- -via file 85
- 3.2 Format of source lines 86
- 3.4 Built-in variables 88
- 3.5 Symbols 90
- Assembler Reference 100
- 3.6.10 Unary operators 104
- Table 3-10 Boolean operators 109
- Operator Usage Explanation 109
- Logical AND of A and B 109
- Logical OR of A and B 109
- Chapter 4 111
- ARM Instruction Reference 111
- 4.1 Conditional execution 114
- Figure 4-1 ROR 135
- Figure 4-2 RRX 136
- Architectures 145
- Examples 145
- Incorrect example 145
- 4.4 ARM multiply instructions 149
- Incorrect examples 151
- 4.6 ARM branch instructions 167
- SWI{cond} immed_24 182
- SWI 0x123456 182
- MSR CPSR_f, r5 185
- 4.9 ARM pseudo-instructions 188
- MOV r0, r0 194
- Chapter 5 195
- Thumb Instruction Reference 195
- PUSH {reglist} 205
- POP {reglist} 205
- PUSH {reglist, lr} 205
- POP {reglist, pc} 205
- 5.4 Thumb branch instructions 225
- BL label 228
- BL extract 228
- SWI immed_8 231
- SWI 12 231
- 5.6 Thumb pseudo-instructions 233
- MOV r8,r8 237
- Chapter 6 239
- 6.2 Floating-point registers 243
- 6.4 VFP and condition codes 246
- 6.5 VFP system registers 248
- 6.6 Flush-to-zero mode 251
- 6.7 VFP instructions 253
- FSTS s2, [r5] 262
- FLDS s9, fpconst 262
- FNMSCSLE s6, s0, s26 266
- 6.8 VFP pseudo-instruction 276
- Chapter 7 283
- Directives Reference 283
- Example 7-1 287
- Example 7-2 287
- WHILE...WEND 308
- IF...ELSE...ENDIF 308
- 7.6 Reporting directives 326
- 7.7 Miscellaneous directives 331
- Glossary 351
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