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RM0352 I
2
C bus interface
137
10.2.16 I
2
C setup time START condition F/S (I2C_TSUSTA_FST_STD)
Table 86. I
2
C setup time START condition F/S (I2C_TSUSTA_FST_STD)
Address: I2CBaseAddress + 0x058
Type: RW
Reset: 0x001D00E2
Description: The I2C_TSUSTA_FST_STD register, that controls the SETUP time START
condition for F/S mode. The register is read-write.
10.2.17 SMBUS slave control register (I2C_SMB_SCR)
Table 87. SMBUS slave control register (I2C_SMB_SCR)
Address: I2CBaseAddress + 0x060
Type: RW
Reset: 0x00000000
Description: SMBUS slave control register (SMBUS MODE)
Note: The LENGTH is used in the slave transmitter to send PEC and in the slave receiver to check
PEC when the I2C_CR:SMBUS = '1' and I2C_CR:ENPEC = '1'.
The PEC is not included: i.e LENGTH = SIZE-OF (data, command, Byte count).
I
2
C setup time START condition F/S (I2C_TSUSTA_FST_STD)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED I2C_TSUSTA_FST RESERVED I2C_TSUSTA_STD
RRWRRW
[24:16] I2C_TSUSTA_FST: setup time START condition value for fast mode
according to fast mode. Once the counter is expired the START condition is
generated.
[8:0] I2C_TSUSTA_STD: setup time START condition value for standard mode.
After a non-stop in SCL line the decimeter loads the value of the
I2C_TSUSTA_STD according to standard mode. Once the counter is expired
the START condition is generated.
SMBUS slave control register (I2C_SMB_SCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LENGTH DSA7 DUAL
RRWRWRW
[18:8] LENGTH: The I2C_SMB_SCR registers transaction length. Defines the
length, in terms of number of bytes to be transmitted or received. In case of
read-from-slave operation or write-to- slave.
- Reference manual 1
- Contents 2
- DocID024647 Rev 1 3/138 3
- 4/138 DocID024647 Rev 1 4
- DocID024647 Rev 1 5/138 5
- 6/138 DocID024647 Rev 1 6
- List of tables 7
- 8/138 DocID024647 Rev 1 8
- DocID024647 Rev 1 9/138 9
- List of figures 10
- 1 Referenced document 11
- 2 System and memory overview 12
- 2.2 Memory organization 13
- 2.3 Embedded SRAM 15
- 2.4 Flash memory overview 15
- 2.5 Physical remap 16
- Interrupts RM0352 18
- Table 3. Interrupt vectors 18
- (continued) 18
- 5.1 Introduction 21
- 5.2 Clock generation 21
- Figure 2. Clock generation 22
- DocID024647 Rev 1 23/138 23
- 5.3 Reset generation 24
- 5.3.2 Power-on reset 25
- 5.3.3 ECC reset 25
- 5.3.4 Watchdog reset 25
- 5.3.5 System reset request 26
- 5.3.6 Lockup reset 26
- 5.3.7 Recall done 26
- 6.3.4 Command register 34
- MASS ERASE 34
- DocID024647 Rev 1 37/138 37
- 0-Unlocked 37
- 1NoLocked 37
- 1 Yes Unlocked 37
- Watchdog timer (WDG) RM0352 40
- Table 26. WDG register list 40
- dual timer module (SP804) 47
- 8.2 Functional overview 48
- DocID024647 Rev 1 49/138 49
- 8.2.2 Functional description 50
- Free running counter blocks 51
- Interface reset 51
- Prescaler operation 52
- Timer operation 53
- 54/138 DocID024647 Rev 1 54
- Interrupt behavior 55
- 56/138 DocID024647 Rev 1 56
- 8.3 Programmer's model 57
- 8.3.2 Register descriptions 59
- Load register, TimerXLoad 60
- ". 63
- 9.4 Configuring SysTick 70
- C bus interface RM0352 72
- Table 70. I 72
- C register list 72
- 74/138 DocID024647 Rev 1 74
- DocID024647 Rev 1 75/138 75
- 76/138 DocID024647 Rev 1 76
- 78/138 DocID024647 Rev 1 78
- 10.2.5 I 80
- C status register (I2C_SR) 80
- DocID024647 Rev 1 81/138 81
- 82/138 DocID024647 Rev 1 82
- DocID024647 Rev 1 87/138 87
- DocID024647 Rev 1 89/138 89
- 90/138 DocID024647 Rev 1 90
- DocID024647 Rev 1 91/138 91
- 11.1 Features 100
- 11.2 Clock prescaler 100
- 101
- 11.5.4 SSPRTINTR 114
- 11.5.1 SSPRXINTR 114
- 11.5.2 SSPTXINTR 114
- 11.5.3 SSPRORINTR 114
- 12.1 Features 115
- 12.2 IrDA SIR block 116
- 12.3 Baud rate generator 116
- 12.4 Interrupts 116
- 12.4.1 UARTMSINTR 117
- 12.4.2 UARTRXINTR 117
- 12.4.3 UARTTXINTR 117
- 12.5 UART registers 118
- 12.6 Register descriptions 120
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