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System Control Coprocessor

ID013010 Non-Confidential, Unrestricted Access

4.2.14 c0, Cache Size Selection Register

The Cache Size Selection Register holds the value that the processor uses to select the Current

Cache Size Identification Register to use.

The Cache Size Selection Register is:

• a read/write register

• accessible in Privileged mode only.

Figure 4-26 shows the bit arrangement for the Cache Size Selection Register.

Figure 4-26 Cache Size Selection Register format

Table 4-22 shows how the bit values correspond with the Cache Size Selection Register.

To access the Current Cache Size Identification Registers read or write CP15 with:

MRC p15, 2, <Rd>, c0, c0, 0 ; Read Cache Size Selection Register

MCR p15, 2, <Rd>, c0, c0, 0 ; Write Cache Size Selection Register

4.2.15 c1, System Control Register

The System Control Register provides control and configuration information for:

• memory alignment, endianness, protection, and fault behavior

• MPU and cache enables and cache replacement strategy

• interrupts and the behavior of interrupt latency

• the location for exception vectors

• program flow prediction.

The System Control Register is:

• a read/write register

• accessible in Privileged mode only.

Figure 4-27 on page 4-36 shows the arrangement of bits in the register.

Reserved Level

43 10

InD

Table 4-22 Cache Size Selection Register bit functions

Bits Field Function

[31: 4] Reserved SBZ.

[3:1] Level Identifies which cache level to select.

b000 = Level 1 cache

This field is read only, writes are ignored.

[0] InD Identifies instruction or data cache to use.

1 = instruction

0 = data.

1 2 ... 114 115 116 117 118 119 120 121 122 123 124 ... 455 456

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